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25.3.7.8 Adjustment
By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential
mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read
as 0. By setting ADJ in ADCn_SINGLECTRL/ADCn_SCANCTRL, the results are left adjusted as shown
in Table 25.4 (p. 350) . When left adjusted, the MSB is always placed on bit 15 and sign extended to
bit 31. All bits below the conversion result are read as 0 (zero).
Table 25.4. ADC Results Representation
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
8
6
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
6
5
5
5
4
4
3
3
2
2
1
1
0
0
OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
12 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
8
6
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
7
5
6
4
5
3
4
2
3
1
2
0
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OVS 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
25.3.8 Interrupts, PRS Output
The single and scan modes have separate interrupt flags indicating finished conversions. Setting one of
these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN.
In addition to the finished conversion flags, there is a scan and single sample result overflow flag which
signalizes that a result from a scan sequence or single sample has been overwritten before being read.
A finished conversion will result in a one HFPERCLK cycle pulse which is output to the Peripheral Reflex
System (PRS).
25.3.9 DMA Request
The ADC has two DMA request lines, SINGLE and SCAN, which are set when a single or scan
conversion has completed. The request are cleared when the corresponding single or scan result register
is read.
25.3.10 Calibration
The ADC supports offset and gain calibration to correct errors due to process and temperature variations.
This must be done individually for each reference used. The ADC calibration (ADCn_CAL) register
contains four register fields for calibrating offset and gain for both single and scan mode. The gain and
offset calibration are done in single mode, but the resulting calibration values can be used for both single
and scan mode.
Gain and offset for the 1V25, 2V5 and VDD references are calibrated during production and the
calibration values for these can be found in the Device Information page. During reset, the gain and
offset calibration registers are loaded with the production calibration values for the 1V25 reference.
The SCANGAIN and SINGLEGAIN calibration fields are not used when the unbuffered differential
2xVDD reference is selected.
2011-04-12 - d0001_Rev1.10
350
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